Ever since the first appearance of amorphous silicon (a-Si) thin-film transistors (TFT)-liquid crystal displays (LCDs) in notebook personal computers more than ten years ago, the number of applications for (a-Si) TFT-LCD has expanded. Fueling this expansion is the increase in screen area and the resolution of (a-Si) TFT-LCD-based display devices. Presently, (a-Si) TFT-LCD-based display devices are found in notebook PCs, modern desktop monitors, televisions, and advanced game equipment. Although the major application of the TFT technology is currently in LCDs, there are many other microelectronic products that could benefit from (a-Si) thin-film transistor technology. For example, a large-area x-ray imager has been successfully fabricated by integrating (a-Si) TFTs with p-i-n photodiodes over a glass substrate coated with an x-ray converter material. High-resolution phantoms of the foot and the head can be recorded with this type of imager. In addition, p-channel TFTs have been used to replace high-resistance loads in static random access memory (SRAM) devices, leading to improved cell stability, low standby current, and reduced cell area. In another example, high-density and high-response-speed printer and fax machines fabricated with TFTs have also been demonstrated. By varying the gate-metal material and the operating conditions, the TFT can be used as a chemical sensor, e.g., to detect changes in gas-phase hydrogen concentration or liquid-phase potassium concentration. Many other devices based on TFT technology, such as the artificial retina or the EEPROM, have also been demonstrated.
The expansion of the role of (a-Si) TFT-based displays in electronic devices has required improvements in the size of the glass substrate used in such displays as well as the production of ever smaller individual TFT structures. The configuration of a typical TFT-LCD-based display, an active matrix display, is shown in FIG. 1. The display operates in the transmission mode with a fluorescent lamp 102 behind panel 104. The panel consists of two glass plates: the bottom and top glass substrates (106, 108). Liquid crystal material is injected between these two glass plates, filling a small gap (on the order of several micrometers) with extreme uniformity. In general, twisted nematic (TN) LC mode is used, so the panel needs a polarizer film 112, 114 on the outer surface of each glass substrate.
Each pixel of the display is driven by an individual a-Si TFT. In FIG. 1, the TFTs are arranged in an x-y matrix formed on the bottom glass substrate. Each TFT operates as an analogue switch to control the stored charge in an LC capacitor defined between an electrode on the bottom substrate and a common electrode on the top substrate. A color filter layer on the top glass substrate consists of three primary chromaticities: red, green, and blue. Each pixel electrode is aligned with a single color of the color filter layer.
While the display-performance and screen size of TFT-LCD displays keeps improving, a critical problem in the TFT-LCD market is the cost of manufacturing such displays. Cost improvements are needed before TFT-LCD displays can effectively replace cathode ray tube based displays in many markets. One approach to lowering manufacturing costs is to fuse the color filter and the TFT array together. See, for example, Sakamoto et al., 1999, AM-LCD Digest, p. 193; Maruyama et al., 1999, EuroDisplay '99, Late-news Digest, p. 77; Hayama et al., 2000, SID '00 Digest, p. 1112; Song et al., 2000, SID '00 Digest, p. 1018. While the technique of fusing the color filter and the TFT array together is beneficial because of lower production costs, the technique imposes limitations on the manner in which the TFT array can be built. Color filters are typically made from organic materials. Because of the sensitivity of organic materials to temperature, the color filter cannot withstand temperatures exceeding 300° C. for any appreciable amount of time. In order to improve the process window for fused TFT array/color filters, Hong et al. report a thermally resistant color filter that can withstand temperatures up to 300° C. However, even with thermally stable color filters such as those reported by Hong et al., the TFT array must be built using deposition techniques that do not require susceptor temperatures exceeding 300° C. This temperature limitation is a drawback because conventional TFT manufacturing techniques rely on susceptor temperatures that are above the temperature limits for even the previously discussed high temperature color filter. Substrate temperature will be lower than susceptor temperature since the susceptor is the actively heated element in a standard chamber, such as the AKT 1600 PECVD (Applied Materials, Santa Clara, Calif.). How much lower depends on the process and hardware conditions. Use of susceptor temperatures substantially below 400° C. results in less desirable TFT performance characteristics. It is likely that these less desirable performance characteristics can be correlated with film properties, such as gate insulator peeling, gate insulator layers with reduced insulating qualities, as well as reduced phosphine incorporation in the source and drain regions of the TFT. These undesirable results are better understood by first examining the structure of a typical TFT.
There are several types of TFTs that may be used in display devices. These types include coplanar TFTs, staggered TFTs, semi-staggered TFTs, reverse staggered TFTs (inverted staggered bilayers or inverted staggered trilayers), back-channel-etched inverted staggered structures. Staggered bilayers and inverted staggered trilayers are discussed in Hiranaka et al., 1989, Jpn. J. Appl. Phys. 28, 2197; and Kuo, 1991, J. Electrochem. Soc. 138, p. 637. Back-channel-etched inverted staggered structures are discussed in Cheng, 1997, J. ElectroChem Soc. 144, p. 2929. FIG. 2 shows a cross-sectional view of a reverse-staggered TFT. This TFT has a gate electrode 202 formed on a substrate 201. Optionally, the entire surface of the gate electrode 202 is covered with an anodic oxide film 203. A gate insulating film 204 is formed on top of gate 202. A polycrystalline or amorphous silicon film 205 is formed over the gate insulating film 204. The TFT is completed by forming source region 209a and a drain region 209b, which are doped with impurity ions, as well as a channel region 209, which is not doped with impurity ions. The channel region 209 is interposed between the source region 209a and the drain region 209b and formed opposite the gate electrode 202. An insulating protective film 206a is formed above the channel region 209, while a source electrode 210a and a drain electrode 210b are formed on the source region 209a and the drain region 209b, respectively.
Depending on the gate metal used in the TFT and the substrate temperature during processing, lower substrate temperatures result in poor adhesion of the gate insulating film 204 on the gate metal 202 (FIG. 2). Subsequent peeling of the gate insulating film 204 compromises the insulating properties of the film.
Another reason low-temperature processing is not desirable is that such processing results in a decrease in substrate temperature relative to conventional deposition processes. This decrease in surface temperature yields a gate insulating film having a lower density. Low density gate insulating films have poorer insulating qualities relative to high density gate films and, as a consequence, they are undesirable.
Yet another consequence of using reduced processing temperatures, at least in the case of CVD deposition, is poor phosphine incorporation into the source and drain regions of the TFT. A variety of methods are used for forming the TFT source and drain regions. In one method, a SiH4 gas containing an impurity gas, such as a PH3 gas, is decomposed by discharge to deposit a n+ a-Si film, thereby forming the source and drain regions. In another method, a gas containing impurities, such as a hydrogen diluted PH3 gas, is ionized by discharge and the resulting ions are accelerated and implanted into an a-Si film without mass separation in order to form a doped film, such as a n+ a-Si film, thereby forming the source and drain regions. This method is referred to as an ion shower doping method and is described in, for example, Japanese Patent Laid-Open Publication Nos. 63-194326, 4-39967, 5-243270, and 6-37110. Other techniques for phosphorous doping are disclosed in U.S. Pat. No. 5,576,229 to Murata et al. However, conventional phosphorous doping is more difficult at low temperatures. This is evidenced by higher resistivity in the source and drain regions of the TFT. To circumvent this problem, higher PH3 concentrations in the feed gas may be used during ion implantation to compensate for the reduced phosphine incorporation. However, in many situations, even the use of higher PH3 amounts in the feed gas is insufficient to increase conductivity.
Given the above background, there is a need in the art to compensate for the decreased TFT performance with CVD films grown at lower than typical temperatures. In particular, there is a need in the art for improving the adhesion of the gate insulating film on the gate metal, improving the electrical characteristics of the gate insulating film, improving the resistivity of the TFT source and drain regions, and improving TFT stress characteristics.